WARP v3 Kit

Due to limited available of key components, the WARP v3 hardware has moved to Last Time Buy status. We will continue to accept orders until inventory is exhausted.

Mango's support of WARP v3 will continue via the 802.11 and WARPLab Reference Designs.

Please contact us with any questions.

WARP v3 is the latest generation of WARP hardware, integrating a high performance FPGA, two flexible RF interfaces and multiple peripherals to facilitate rapid prototyping of custom wireless designs.

Hardware Features

The hardware features of WARP v3 are listed below. For full details please see the WARP v3 User Guide.
  • Xilinx Virtex-6 LX240T FPGA
  • 2 programmable RF interfaces, each with:
    • 2.4/5GHz transceiver (40MHz RF bandwidth)
    • 12-bit 170MSps DACs, 12-bit 100MSps ADCs
    • Dual-band PA (20dBm Tx power)
    • Shared clocking for MIMO applications
  • FMC HPC expansion slot
  • 2 gigabit Ethernet interfaces
  • DDR3 SO-DIMM slot
  • FPGA config via JTAG, SD card or flash
  • User I/O:
    • USB-UART
    • 12 LEDs
    • 2 seven-segment displays
    • 4 push buttons
    • 4-bit DIP switch
    • 16-bit 2.5v I/O header

Reference Designs

We provide a number of open-source reference designs which provide excellent starting points for research projects on WARP v3.

  • The Mango 802.11 Reference Design implements the MAC and PHY from 802.11a/g entirely on the WARP v3 node. This design interoperates with commercial Wi-Fi devices in real time. The MAC and PHY source code are provided with the design allowing researchers to customize behaviors at any layer and evaluate their extensions in real networks. The 802.11 Reference Design is available only on Mango WARP v3 hardware.

  • The WARPLab Reference Design enables rapid PHY prototyping using WARP hardware for waveform Tx/Rx and MATLAB for signal processing.

  • The OFDM Reference Design implements a flexible OFDM PHY and CSMA MAC in the WARP v3 FPGA. This design interoperates with similar designs in previous generations of WARP hardware.

Researchers can also build their custom wireless designs from scratch. We provide a number of open-source support cores which facilitate use of the WARP v3 peripherals and I/O interfaces in custom designs.

Add-on Boards

The WARP v3 hardware can be extended with additional I/O and processing resources via the FMC and Clock Module slots.
  • FMC-RF-2X245: Dual-radio FMC module, extends the WARP v3 node to 4-antennas
  • FMC-BB-4DA: Quad-DAC FMC module, adds 4 baseband analog outputs
  • CM-MMCX: Clock module with MMCX connectors, enables sharing clocks between WARP v3 nodes
  • CM-PLL: Clock module with PLL & VCXO, enables simple synchronization of multiple WARP v3 nodes

Many third-party FMC modules are also available.

Kit Contents

The Mango WARP v3 kit contains:
  • WARP v3 board (hardware rev 1.1)
  • SD card (pre-formatted)
  • Power supply (100-240VAC to 12VDC)
  • 2 50-ohm SMA terminators

The WARP v3 kit does not include antennas or RF cables. The RF connectors on WARP v3 are 50-ohm SMA jacks (standard polarity and gender). A wide variety of compatible RF accessories are available from third parties. We have heard good things about antennas from L-com and cables/attenuators from Pasternack and Crystek.

The WARP v3 kit also does not include a JTAG programming cable. We recommend the Digilent XUP-USB-JTAG or JTAG-HS2. Both are supported by the Xilinx tools and connect directly to the JTAG connector on the WARP v3 board. It is possible to configure the WARP v3 FPGA using only the SD card. However we strongly recommend having a JTAG cable to enable real-time debugging via the Xilinx SDK and ChipScope Analyzer.

Pricing & Availability

Pricing starts at US$4900 for academic customers. Please see the Mango Price List for the complete pricing and availability.

Additional Documentation


Please contact us with any questions.